Zero capacitor memory
technology is proved
realisable for FinFET and
TriGate device geometries

A new paper recently given by Innovative Silicon Inc. (ISi), claims to prove the manufacturability of its Z-RAM (zero capacitor) embedded memory technology in FinFET and TriGate devices with geometries below 45nm.

Z-RAM memory arrays have already been successfully demonstrated on silicon using partially depleted SOI structures, and the experimental results presented in this new paper ensure that the technology will scale to 45nm and beyond.

In the recently-introduced Z-RAM floating body memory cell, the conventional storage capacitor is replaced by the body capacitance of a SOI MOSFET. The charge stored in the floating body affects the device threshold voltage through the body effect and can be used to distinguish two states. This eliminates the need for a capacitor element, so the resulting memory cell structure is based solely on a single transistor. Therefore, Z-RAM memories can achieve five times the density of embedded SRAM and twice the density of embedded DRAM designs.

For the first time, new experimental work by ISi shows that good retention characteristics for a Z-RAM memory cell based on CMOS FinFET and Tri-Gate devices can be measured.