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Complete 667Mbps DDR/DDR2 SDRAM Structured ASIC announced A complete DDR/DDR2 SDRAM solution with speeds up to 667Mbps, including a DDR/DDR2 PHY; and DDR/DDR2 SDRAM Controller Cores for use on all CX6000 Structured ASIC products, has been annouced by , Structured ASIC Leader, and Northwest Logic. All DDR/DDR2 SDRAM chip designs require close integration of the physical interface (PHY) with both the chip process and the memory controller core, to meet tight memory timing requirements. Third-party PHY designs often require extensive custom engineering to meet performance specifications of a given process, and often do not integrate well with the target memory controller core, presenting a significant challenge to the chip designer. The ChipX solution solves this design challenge by offering a DDR/DDR2 PHY design built entirely out of logic cells (XCells ™) on the CX6000 130nm family of Structured ASIC products. This PHY has been integrated and verified with the configurable memory controller cores from Northwest Logic. The ChipX DDR/DDR2 PHY can be placed next to any CX6000 I/O bank and supports any bus width in 8-bit increments. Because the PHY design is implemented as an overlay and does not reside in the basic gates, there is no penalty if it is not placed. |
Northwest Logic DDR and DDR2 Memory Controller Cores provide extremely high bus efficiency using Request Reordering, Bank Management and Look-Ahead processing. The cores can also be configured during design or real-time to work with any memory configuration. Northwest Logic also provides separate ECC, Read-Modify-Write, and Multi-Port Front-End add-on modules to enable each design to be optimally configured. The cores support the very high memory clock rates and have a minimal gate count
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